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LG Semicon Co.,Ltd.
GM71V65163A GM71VS65163AL
4,196,304 WORDS x 16 BIT CMOS DYNAMIC RAM
Description
The GM71V(S)65163A/AL is the new generation dynamic RAM organized 4,196,304 words by 16 bits. The GM71V(S)65163A/AL utilizes advanced CMOS Silicon Gate Process Technology as well as advanced circuit techniques for wide operating margins, both internally and to the system user. System oriented features include single power supply of 3.3V+/-10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL. The GM71V(S)65163A/AL offers Extended Data Out(EDO) Mode as a high speed access mode.
Pin Configuration 50 SOJ / TSOP
VCC IO0 IO1 IO2 IO3 VCC IO4 IO5 IO6 IO7 NC VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 VSS IO15 IO14 IO13 IO12 VSS IO11 IO10 IO9 IO8 NC VSS /LCAS
Features
* 4,196,304 Words x 16 Bit * Extended Data Out (EDO) Mode Capability * Fast Access Time & Cycle Time (Unit: ns)
/WE /RAS NC NC NC NC A0 A1
37 /UCAS 36 35 34 33 32 31 30 29 28 27 26 /OE NC NC NC A11 A10 A9 A8 A7 A6 VSS
tRAC
GM71V(S)65163A/AL-5 GM71V(S)65163A/AL-6 50 60
tAA
25 30
tCAC
13 15
tRC
90 110
tHPC
20 25
A2 A3 A4 A5 VCC
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*Power dissipation - Active : 720mW/648mW(MAX) - Standby : 1.8 mW ( CMOS level : MAX ) 0.54mW ( L-Version : MAX) *EDO page mode capability *Access time : 50ns/60ns (max) *Refresh cycles - RAS only Refresh 4096 cycles/64 A (GM71V65163A) 4096 cycles/128A (GM71VS65163AL)(L_Version) *CBR & Hidden Refresh 4096 cycles/64 A (GM71V65163A) 4096 cycles/128 A (GM71VS65163AL)( L-Version ) *4 variations of refresh -RAS-only refresh -CAS-before-RAS refresh -Hidden refresh -Self refresh (L-Version) *Single Power Supply of 3.3V+/-10 % with a built-in VBB generator *Battery Back Up Operation ( L-Version )
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Pin Description
Pin A0-A11 A0-A11 RAS UCAS,LCAS OE Function Address Inputs Refresh Address Inputs Row Address Strobe Column Address Strobe Output Enable Pin WE I/O0 - I/O15 VCC VSS NC
GM71V65163A GM71VS65163AL
Function Write Enable Data Input / Output Power (+3.3V) Ground No Connection
Ordering Information
Type No. GM71V(S)65163A/ALJ-5 GM71V(S)65163A/ALJ-6 GM71V(S)65163A/ALT-5 GM71V(S)65163A/ALT-6 Access Time 50A 60A 50A 60A Package 400 Mil 50 Pin Plastic SOJ 400 Mil 50 Pin Plastic TSOP II
Absolute Maximum Ratings*
Symbol TSTG VT VCC IOUT PT Parameter Storage Temperature (Plastic) Voltage on any Pin Relative to VSS Voltage on VCC Relative to VSS Short Circuit Output Current Power Dissipation Rating -55 to 125 -0.5 to VCC + 0.5 (MAX ; 4.6V) -0.5 to 4.6 50 1.0 Unit C V V mA W
*Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol VCC VSS VIH VIL TA Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Ambient Temperature under Bias Min 3.0 0 2.0 -0.3 0 Typ 3.3 0 Max 3.6 0 Vcc+0.3 0.8 70 Unit V V V V C Notes 1,2 2 1 1
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Symbol VOH VOL ICC1 Parameter Output Level Output Level Voltage (IOUT = -2mA) Output Level Output Level Voltage (IOUT = 2mA) Operating Current (tRC = tRC min) 50ns 60ns ICC2 Standby Current (TTL interface) Power Supply Standby Current (RAS, UCAS,LCAS= VIH, DOUT = High-Z) RAS-Only Refresh Current ( tRC = tRC min) Extended Data Out page Mode Current (RAS = VIL, CAS, Address Cycling: tHPC = tHPC min) CMOS interface (RAS, UCAS,LCAS>=VCC-0.2V, DOUT = HighZ) Standby Current(L_Version) CAS-before-RAS Refresh Current (tRC = tRC min) 50ns 60ns 50ns 60ns 50ns 60ns
GM71V65163A GM71VS65163AL
Min 2.4 0 Max VCC 0.4 200 180 2 mA Unit V V mA 1,2 Note
DC Electrical Characteristics: (VCC = 3.3V+/-10%, TA = 0 ~ 70C)
ICC3
-
200 180 120 mA 110 0.5 mA 1,3 mA 2
ICC4
ICC5
-
300 160 140 500
uA mA uA
4
ICC6
ICC7 ICC8
Battery Back Up Operating Current(Standby with CBR) (tRC=31.25us,,tRAS=300ns,Dout=High-Z) Standby Current (CMOS) Power Supply Standby Current RAS = VIH,UCAS, LCAS = VIL , DOUT = Enable Self Refresh Current (RAS,UCAS,LCAS <=0.2V,Dout=High-Z) Input Leakage Current, Any Input (0V<=VIN<=Vcc) Output Leakage Current (DOUT is Disabled, 0V<=VOUT<=Vcc)
4, 5
-
5
mA
1 5
ICC9 II(L) IO(L)
-5 -5
400 5 5
uA uA uA
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, tHPC. 4. VIH>=VCC-0.2V, 0V<=VIL<=0.2V 5. L-version
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Capacitance (VCC = 3.3V+/-10%, TA = 25C)
Symbol CI1 CI2 CI/O Parameter Input Capacitance (Address) Input Capacitance (Clocks) Output Capacitance (Data-in,Data-Out) Typ -
GM71V65163A GM71VS65163AL
Max 5 7 7 Unit U U U Note 1 1 1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS, UCAS and LCAS = VIH to disable DOUT.
AC Characteristics (VCC = 3.3V+/-10%, TA = 0 ~ 70C, Notes 1,2,19,20)
Test Conditions Input rise and fall times : 2ns Output timing reference levels : VOL/VOH = 0.8/2.0V Input level : VIL/VIH = 0.0/3.0V Output load : 1 TTL gate+CL (100pF) Input timing reference levels : VIL/VIH = 0.8/2.0V (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol
Parameter
Random Read or Write Cycle Time RAS Precharge Time CAS Precharge Time RAS Pulse Width CAS Pulse Width Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time RAS to CAS Delay Time RAS to Column Address Delay Time RAS Hold Time CAS Hold Time CAS to RAS Precharge Time OE to DIN Delay Time OE Delay Time from DIN CAS Delay Time from DIN TransitionTime (Rise and Fall) Refresh Period Refresh Period ( L-Version )
GM71V(S)65163A/AL-5 GM71V(S)65163A/AL-6
Min
Max
10000 10000 37 25 50 64 128
Min
104 40 10 60 10 0 10 0 10 14 12 17 40 5 15 0 0 2 -
Unit
Notes
Max
10000 10000 45 30 50 64 128 A A A A A A A A A A A A A A A A A A A A 22 5 6 6 7
4096 cycles 4096 cycles
tRC tRP tCP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tDZO tDZC tT tREF
84 30 8 50 8 0 8 0 8 12 10 13 35 5 13 0 0 2 -
24
21 21 3 4
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Read Cycles
GM71V65163A GM71VS65163AL
GM71V(S)65163A/AL-5 GM71V(S)65163A/AL-6
Symbol
Parameter
Min Max
50 13 25 13 13 13 13 13 -
Unit
Notes
Min
0 0 0 30 18 15 15 15 3 3 60 3 0
Max
60 15 30 15 15 15 15 15 A A A A A A A A A A A A A A A A A A A A A
tRAC tCAC tAA tOAC tRCS tRCH tRRH tRAL tCAL tOFF tOEZ tCDD tRDD tWDD tOFR tWEZ tOH tOHR tRCHR tOHO tCLZ
Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from OE Read Command Set-up Time Read Command Hold Time to CAS Read Command Hold Time to RAS Column Address to RAS Lead Time Column Address to CAS Lead Time Output Buffer Turn-off Delay Time from CAS Output Buffer Turn-off Delay Time from OE CAS to DIN Delay Time RAS to DIN Delay Time WE to DIN Delay Time Output Buffer Turn-off Delay Time from RAS Output Buffer Turn-off Delay Time from WE Output Data Hold Time Output Data Hold Time from RAS Read Command Hold Time from RAS Output data hold time from OE CAS to Output in Low - Z
0 0 0 25 15 13 13 13 3 3 50 3 0
8,9 9,10,17 9,11,17 9 21 12,22 12
13,26 13 5
13,26 13 26 26
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Write Cycles
GM71V(S)65163A/AL-5
GM71V65163A GM71VS65163AL
GM71V(S)65163A/AL-6
Unit Notes
Symbol
Parameter
Min Max
-
Min
0 10 10 17 10 0 10
Max
A A A A A A A 23 15,23 15,23 14,21 21
tWCS tWCH
Write Command Set-up Time Write Command Hold Time Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time
0 8 8 13 8 0 8
tWP
tRWL tCWL tDS tDH
Read-Modify-Write Cycles
Symbol
Parameter
Read-Modify-Write Cycle Time RAS to WE Delay Time CAS to WE Delay Time Column Address to WE Delay Time OE Hold Time from WE
GM71V(S)65163A/AL-5
GM71V(S)65163A/AL-6
Unit Notes
Min
Max
-
Min
140 79 34 49 15
Max
A A A A A 14 14 14
tRWC tRWD tCWD tAWD tOEH
116 67 30 42 13
Refresh Cycle Cycles
GM71V(S)65163A/AL-5 GM71V(S)65163A/AL-6
Unit Notes
Symbol
Parameter
CAS Set-up Time (CAS-before-RAS Refresh Cycle) CAS Hold Time (CAS-before-RAS Refresh Cycle) WE setup time (CAS-before-RAS Refresh Cycle) WE hold time (CAS-before-RAS Refresh Cycle) RAS Precharge to CAS Hold Time
Min
5 8 0
Max
-
Min
5
Max
A 21
tCSR tCHR tWRP tWRH tRPC
-
10 0
-
A A
22
8 5
-
10 5
-
A A 21
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Extended Data Out Mode Cycles
Symbol
GM71V65163A GM71VS65163AL
GM71V(S)65163A/AL-5 GM71V(S)65163A/AL-6
Parameter
Min Max
100000 28 -
Unit
Notes
Min
25 10 35 10 5 35
Max
100000 35 A A A A A A A A A A 25
tHPC tWPE tRASP tACP tRHCP tCOL tCOP tRCHP tDOH tOEP
EDO Page Mode Cycle Time Write pulse width during CAS Precharge EDO Mode RAS Pulse Width Access Time from CAS Precharge RAS Hold Time from CAS Precharge CAS Hold Time Referred OE CAS to OE set-up Time Read Command Hold Time from CAS Precharge Output Data Hold Time from CAS Low OE Precharge Time
20 8 28 8 5 28
16 9,17,22
3 8
-
3 10
-
9,27
EDO Page Mode Read-Modify-Write cycle
GM71V(S)65163A/AL-5 GM71V(S)65163A/AL-6
Symbol
Parameter
Min Max
-
Unit
Notes
Min
68 54
Max
A A 14,22
tHPRWC EDO Read-Modify-Write Cycle Time tCPW
EDO Page Mode Read-Modify-Write Cycle CAS Precharge to WE Delay Time
57 45
Self Refresh Cycles (L_Version)
GM71V(S)65163A/AL-5 GM71V(S)65163A/AL-6
Symbol
Parameter
RAS Pulse Width(Self-Refresh) RAS Prechartge Time(Self-Refresh) CAS Hold Time(Self-Refresh)
Min
100 90 -50
Max
-
Min
100 110 -50
Max
-
Unit us us us
Notes 31 31 23
tRASS tRPS tCHS
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Notes:
1. 2. AC measurements assume tT = 2A.
GM71V65163A GM71VS65163AL
AC initial pause of 200us is required after power up followed by a minimum of eight initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-beforeRAS refresh) Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only: if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a reference point only: if tRAD is greater than the specified tRAD(max) limit, then access time is controlled exclusively by tAA. Either tODD or tCDD must be satisfied. Either tDZO or tDZC must be satisfied. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH(min) and VIL (max). Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. Assumes that tRCD>=tRCD(max) and tRCD + tCAC(max) >=tRAD + tAA(max). Assumes that tRAD >=tRAD (max) and tRCD + tCAC(max)<=tRAD + tAA(max). Either tRCH or tRRH must be satisfied for a read cycles. tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels. tWCS, tRWD, tCWD, tAWD, and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if tWCS >=tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) and tCPW>=tCPW(min), the cycle is a readmodify-write and the data output will contain data read from the selected cell: if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. tDS and tDH are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. tRASP defines RAS pulse width in extended data out mode cycles. Access time is determined by the longest among tAA, tCAC and tACP. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of UCAS or LCAS. tCRP, tCHR, tRCH, tACP and tCPW are determined by the later rising edge of UCAS or LCAS.
3.
4.
5. 6. 7. 8. 9. 10. 11. 12. 13. 14.
15. 16. 17. 18. 19.
20. 21. 22.
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GM71V65163A GM71VS65163AL
23. tCWL, tDH, tDS and tCHS should be satisfied by the both UCAS and LCAS. 24. tCP is determined by the time that both UCAS and LCAS are high. 25. tHPC(min) can be achieved during a series of EDO mode early write cycles or EDO mode read cycles. If both write and read operation are mixed in a EDO mode, RAS cycle { EDO mode mix cycle (1),(2) } minimum value of CAS cycle tHPC(tCAS + tCP + 2tT) becomes greater than the specified tHPC(min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 26. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between tOHR and tOH, and between tOFR and tOFF. 27. tDOH defines the time at which the output level go cross. VOL=0.8V, VOH=2.0V of output timing reference level. 28. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64A period on the condition a and b below. a. Enter self refresh mode within 15.6us after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b. Start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6us after exiting from self refresh mode. 29. In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and after self refresh mode according as note 28. 30. For L_Version, it is available to apply each 128A and 31.2us instead of 64A and 15.6us at note 28. 31. At tRASS3/4100 us , self refresh mode is activated, and not active at tRASS 1/410us. It is undefined within the range of 10 us 1/4tRASS 1/4100 us . for tRASS 3/410 us , it is necessary to satisfy tRPS. 32. XXX: H or L ( H : VIH(min)<=VIN<=VIH(max), L: VIH(min)<=VIN<=VIH(max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
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Timing Waveforms
tRC tRAS
RAS
GM71V65163A GM71VS65163AL
tRP
tCSH tRCD tT
UCAS LCAS
tCRP tRSH tCAS
tRAD tASR
ADDRESS
tRAH
ROW
tASC
tRAL tCAL tCAH
COLUMN
tRCHR tRCS
WE
tRRH tRCH
tCAC tAA tCLZ
High-Z
tOFF
DOUT
tWEZ
DOUT
tRAC tOH tOEZ tOHO tDZC
DIN High-Z
tOFR tRDD tOHR tWDD
tCDD
tDZO
OE
tOAC
tODD
FIGURE 1. READ CYCLE*32
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GM71V65163A GM71VS65163AL
tRC tRAS
RAS
tRP
tT
tRSH tRCD tCSH tCAS tCRP
UCAS LCAS
tASR
ADDRESS
tRAH
ROW
tASC
tCAH
COLUMN
tWCS
WE
tWCH
tDS
DIN
DIN
tDH
High-Z DOUT
> * tWCS = tWCS (min)
FIGURE 2. EARLY WRITE CYCLE
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GM71V65163A GM71VS65163AL
tRC tRAS
RAS
tRP
tT
tRSH tRCD tCSH tCAS tCRP
UCAS LCAS
tASR
ADDRESS
tRAH
ROW
tASC
tCAH
COLUMN
tCWL tRCS
WE
tRWL tWP
tDZC
High-Z
tDS
tDH
DIN
DIN
tDZO
tODD tOEP
tOEH
OE
tOEZ tCLZ
High-Z DOUT
INVALID OUTPUT
FIGURE 3. DELAYED WRITE CYCLE*18
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GM71V65163A GM71VS65163AL
tRWC tRAS
RAS
tRP
tT
tRCD
tCAS
tCRP
UCAS LCAS
tRAD tASR
ADDRESS
ROW
tRAH
tASC
tCAH
COLUMN
tRCS tRWD
WE
tCWD tAWD
tCWL tRWL tWP
tAA tRAC tDZC tCAC
High-Z
tDS
tDH
DIN
DIN
tCLZ
High-Z DOUT
tODD
tOEH
DOUT
tOAC tDZO
OE
tOEZ tOHO tOEP
FIGURE 4. READ MODIFY WRITE CYCLE*18
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tRC tRAS
RAS
GM71V65163A GM71VS65163AL
tRP
tCRP
UCAS LCAS
tT
tRPC
tCRP
tASR
ADDRESS
ROW
tRAH
tOFR tOFF
High-Z DOUT
FIGURE 5. RAS ONLY REFRESH CYCLE
tRC tRP
RAS
tRC tRP tRAS tRP
tRAS
tRPC tCP
CAS
tT tCSR tCHR
tRPC tCP tCSR tCHR
tCRP
tWRP
tWRH
tWRP
tWRH
WE
ADDRESS
tOFR tOFF
High-Z DOUT
FIGURE 6. CAS BEFORE RAS REFRESH CYCLE
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GM71V65163A GM71VS65163AL
tRC tRAS
RAS
tRC tRP tRAS tRP tRAS
tRC tRP
tT tRCD
UCAS LCAS
tRSH
tCHR tCAS
tCRP
tRAD tASR
ADDRESS
ROW
tRAL tCAH
COLUMN
tRAH
tASC
tRCS
WE
tRCH tRRH
tDZC
High-Z DIN
tWDD tCDD tRDD
tDZO
OE
tOAC
tODD
tRAC tCLZ
DOUT
tCAC tAA
tOEZ tWEZ tOHO tOFF tOH
DOUT
tOFR tOHR
FIGURE 7. HIDDEN REFRESH CYCLE
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GM71V65163A GM71VS65163AL
tRASP tRP
RAS
tHPC tT tCSH tCP tCAS tRCHR tRCS tRCH tRAL tWDD tASR tRAH tASC
ROW
tHPC tCP tCAS tCAS
tRHCP tCP tRSH tCAS tRCHP
tCRP
UCAS LCAS
tRRH tRCH
WE
tCAH
tWPE tASC
tCAH tASC
tCAH tASC
COLUMN
tCAH
COLUMN
ADDRESS
COLUMN
COLUMN
tCAL tDZC
tCAL
High-Z
tCAL
tCAL
tRDD tCDD
DIN
tDZO
tCOL tOEP
tCOP tOEP tODD
OE
tOAC tCAC tAA tRAC
DOUT
tOEZ tOHO tCAC tAA tWEZ tACP
DOUT 2
tACP tAA tCAC tOAC tOEZ tDOH
DOUT 2
tACP tAA tCAC tOAC
tOHR tOFR tOEZ tOHO tOFF tOH
tOHO
DOUT 3 DOUT 4
High-Z
DOUT 1
FIGURE 8. EXTENDED DATA OUT PAGE MODE READ CYCLE
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GM71V65163A GM71VS65163AL
tRASP tRP
RAS
tCSH tT tCP
LCAS
tHPC tCP tCAS
tHPC
tHPC tCP tRSH tCAS
tCRP
tCAS
UCAS
tCAS tRCS tRCHP tRRH tRCH tRAL tWDD tASR tRAH tASC tCAH
COLUMN
WE
tASC tCAH
COLUMN
tCAH tASC
COLUMN
tASC
tCAH
COLUMN
ADDRESS
ROW
tCAL tDZC
tCAL
tCAL
High-Z
tCAL
tRDD tCDD
DIN
tDZO
tCOL tOEP
tCOP tOEP
tODD
OE
tOAC tCAC tAA tRAC
LDOUT
tACP tAA tCAC tOEZ tOHO tOAC tOEZ tOHO
DOUT 2
tACP tAA tCAC
DOUT 4
tDOH
DOUT 1 DOUT 2
tOFR tOHR tOEZ tOHO tOFF tOH
tACP tAA
UDOUT
DOUT 1
tCAC
DOUT 3
tOAC
DOUT 4
FIGURE 9. EXTENDED DATA OUT MODE READ CYCLE (2CAS CONTROL)
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GM71V65163A GM71VS65163AL
tRP tRASP
RAS
tT tRCD
tCSH tCAS tCP
tHPC tCAS tCP
tRSH tCAS
tCRP
UCAS LCAS
tASR tRAH tASC tCAH tASC tCAH tASC tCAH
ADDRESS
ROW
COLUMN 1
COLUMN 2
COLUMN N
tWCS
WE
tWCH
tWCS
tWCH
tWCS
tWCH
tDS
DIN DIN 1
tDH
tDS
DIN 2
tDH
tDS
DIN N
tDH
High-Z*
DOUT
*tWCS >=tWCS (min)
FIGURE 10. EXTENDED DATA OUT MODE EARLY WRITE CYCLE
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GM71V65163A GM71VS65163AL
tRASP
RAS
tRP
tT tRCD
UCAS LCAS
tCP tCSH tCAS tHPC tCAS
tCP tRSH tCAS
tCRP
tASR
tASC tRAD tRAH tCAH
COLUMN 1
tASC tCAH
COLUMN 2
tASC tCAH
COLUMN N
ADDRESS
ROW
tCWL tRCS
WE
tCWL tRCS tRCS
tCWL tRWL
tWP tDZC tDS tDH
DIN
DIN 1
tWP tDZC tDS tDH
DIN 2
tWP tDZC tDS tDH
DIN N
tDZO tODD tOEH
OE
tDZO tODD tOEH tOEP tCLZ tOEZ tCLZ tOEZ
INVALID DOUT
tDZO tODD tOEH tOEP tCLZ tOEZ
INVALID DOUT
High-Z
DOUT
INVALID DOUT
FIGURE 11. EXTENDED DATA OUT MODE DELAYED WRITE CYCLE*18
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GM71V65163A GM71VS65163AL
tRASP
RAS
tRP
tT tCP tRCD
UCAS LCAS
tHPRWC tRSH tCAS tCP tCAS tCAS
tCRP
tRAD tASR tRAH tASC tCAH
COLUMN 1
tASC tCAH
COLUMN 2
tASC tCAH
COLUMN N
ADDRESS
ROW
tRCS
WE
tRWD tAWD tCWD
tCWL
tCPW tAWD tRCS tCWD
tCWL tRCS
tCPW tAWD tCWD
tCWL tRWL
tWP tDZC tDS tDH
DIN
DIN 1
tWP tDZC tDS tDH
DIN 2
tWP tDZC tDS tDH
DIN N
High-Z
tDZO
tOEP tDZO tODD tOEH tOEZ tOAC tCAC tAA tOHO
tDZO tOEP tODD tOEH tOEZ tOHO tOAC tCAC tAA tCLZ tOEZ tOAC tCAC tAA tCLZ
DOUT 2
tOEP tODD tOEH tOHO
OE
tRAC tCLZ
DOUT
tACP
DOUT 1
tACP
DOUT N
High-Z
FIGURE 12. EXTENDED DATA OUT MODE READ MODIFY WRITE CYCLE*18
20
LG Semicon
GM71V65163A GM71VS65163AL
tRASP
RAS
tRP
tT tRCD tCSH tWCS tWCH
WE
tCP tCAS tCAS
tCP tCAS
tCP tCAS
tCRP
UCAS LCAS
tRCS tCPW tAWD
tWP
tRSH tRAL tASC
tRRH tRCH
tRAH tASR
ADDRESS
ROW
tASC tCAH
COLUMN 1
tASC tCAH
COLUMN 2
tASC tCAH
COLUMN 3
tCAH
COLUMN 4
tDS
Din
tDH
DIN 1
tCAL
High - Z
tDS tDH
DIN 3
tCAL
tRDD tCDD
tODD tOEP
OE
tWDD
tCAC tOAC tAA tACP
Dout
tDOH tAA tACP
DOUT 2
tCAC tOEZ tOHO
DOUT 3
tCAC tAA tOAC tACP
tOFR tOFF tOH
DOUT 4
tWEZ tOEZ
High - Z
FIGURE 13. EXTENDED DATA OUT MODE MIX CYCLE (1)*25
21
LG Semicon
GM71V65163A GM71VS65163AL
tRASP
RAS
tRP
tT tRCD
tCSH tCAS
tCP tCAS
tCP tCAS
tCP tCAS tRSH tRAL tASC tCAH tCAH
COLUMN 4
tCRP
UCAS LCAS
tRCHR tRCS tRCH tWCH tWCS tCPW tASC tCAH
COLUMN 1
tWP
tRRH tRCH
WE
tRAH tASR
ADDRESS
ROW
tASC tCAH
COLUMN 2
tASC
COLUMN 3
tCAL
Din
tCAL tDS tDH
DIN 2
tDS
tCAL tDH
DIN 3
tCAL
tRDD tCDD
High - Z
tODD tOEP
OE
tCOL
tODD tOEP tCOP tOEZ
tWDD
tCAC tAA tOAC tRAC
Dout
tOEZ tOHO
DOUT 1
tCAC tAA tACP tOAC
tCAC tAA tOAC tACP
tOFF tOH tOFR
DOUT 4
tWEZ tOEZ
High - Z
DOUT 3
tOHO
FIGURE 14. EXTENDED DATA OUT MODE MIX CYCLE (2)*25
22
LG Semicon
GM71V65163A GM71VS65163AL
tRP
RAS
tRASS
tRPS
tRPC tCP
LCAS UCAS
tT tCSR
tCHS
tCRP
tWRP
WE
tWRH
tOFR tOFF
High-Z
DOUT
FIGURE 15. SELF REFRESH CYCLE*28,29,30,31
23
LG Semicon
SOJ 50 PIN Package Dimension
GM71V65163A GM71VS65163AL
TSOP 50 PIN Package Dimension
0.40 MIN 0.60 MAX
20.95 MIN 21.35 MAX
0~5
Unit: mm
1.20 MAX
0.145 0.125 0.80
0.30 0.28
0.10 0.08
0.80
0.08 MIN 0.18 MAX
0.10
Dimension including the plating thickness Base material dimension
0.68
1.15 MAX
11.56 MIN
0.05 0.04
11.96 MAX
10.16
24

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